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12/15/97 SS1101C integrated spread-spectrum transceiver (sst) external specification preliminary (v 1.1b)

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2 preliminary v1.1 table of contents 1. introduction ........................................................................................................4 1.1. voice mode ............................................................................................4 1.2. data mode ..............................................................................................4 1.3. general information ...............................................................................4 1.4. main features summary .........................................................................4 2. functional description .......................................................................................5 2.1. pbi .........................................................................................................5 2.2. receiver .................................................................................................5 2.3. transmitter .............................................................................................6 2.4. tdd controller ......................................................................................6 2.5. fifos .....................................................................................................7 2.6. master clock generator .........................................................................7 3. operational description .....................................................................................7 3.1. full-duplex voice and data operations ................................................7 3.1.1 tdd protocol ............................................................................8 3.1.2 system delay ............................................................................10 3.2. voice mode timing information ...........................................................11 3.3. data mode timing information .............................................................12 3.3.1 full duplex operations .............................................................12 3.3.2 threshold value calculation .....................................................12 3.3.3 half-duplex operation ..............................................................13 4. the parallel bus interface ..................................................................................16 4.1. read and write operations ....................................................................16 4.1.1 write operation ........................................................................16 4.1.2 read operation .........................................................................16 4.2. loading of the SS1101C programmable data .......................................17 4.3. reading the sw and s/n data from the pbi .........................................18 4.3.1 signaling word (sw) transmitting ..........................................18 4.3.2 sw receiving ...........................................................................18 5. control, sw, and fifo registers ......................................................................19 5.1. configuration information bits ..............................................................21 5.2. reset .......................................................................................................23 5.3. rf/if analog interface ..........................................................................23 6. i/o description ..................................................................................................26 7. i/o buffer information .......................................................................................29 8. timing information ............................................................................................30 www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary v1.1 3 9. absolute maximum rating ................................................................................30 10. recommended operating conditions ..............................................................30 11. system performance ........................................................................................31 12. pin assignment ................................................................................................32 13. application information ..................................................................................32 13.1. notes on half-duplex operation ...........................................................32 13.2. selecting the master oscillator frequency ..........................................33 13.3. programming the SS1101C .................................................................33 13.4. pn sequence and uw selection ..........................................................36 13.4.1 pn sequence selection ...........................................................36 13.4.2 uw selection ..........................................................................36 13.5. generating the pn and uw sequences ................................................37 13.6. using burst synchronization feature ..................................................37 13.7. example of rf front-end block diagram ..........................................38 www.datasheet.co.kr datasheet pdf - http://www..net/
introduction 4 preliminary v1.1 1. introduction siliconians SS1101C is a low-cost, low-power, multi-purpose spread spectrum communication chip designed to support digital voice or data communications for fcc part 15-compliant wireless devices operating on ism bands (usa), or on any other available frequency band (international). the SS1101C is a very flexible chip for voice applications such as digital cordless phones (dcp) for both consumer or wireless pbxs (w-pbx). in data mode, the chip is usable in acquisition and control applications (scada) as well as high-speed wireless lan applications. it is implemented as a cmos device packaged within an economic low-pin count (44-pin) surface-mounted plastic package. 1.1. voice mode for operation in voice mode, the SS1101C interfaces directly with a 64 kbps pcm codec for land-line quality voice in a low-cost digital cordless phone. it can optionally also interface with a 32 kbps adpcm codec for high-quality compressed voice. this low-cost spread spectrum technology makes monitoring of phone calls practically impossible and greatly extends the range compared with other analog or digital phones operating in the ism bands. 1.2. data mode for operation in data mode, the SS1101C includes all of the modem baseband functions and operates in full-duplex or half-duplex modes. the on-the-air transmission is synchronous and the chip includes flexible dual fifos accessible by any standard microcontroller through a parallel bus and an interrupt mechanism. it provides high speed data capabilities with a maximum half-duplex rate of 400 kbps. in the half-duplex mode, no assumption about the higher level protocols is made, instead, the SS1101C is designed to be flexible and can be configured for a variety of uses. 1.3. general information the SS1101C provides constant monitoring of the link quality with an indication of the relative signal/noise at the baseband level. in data full-duplex and in voice modes, it also provides a low-speed signaling channel (overhead channel) independent of the main data/voice channel. the SS1101C is a 3v/5v cmos device and contains power- saving features, including very low battery drain in standby, for battery operation. 1.4. main features summary ? integrated direct sequence spread spectrum baseband modem ? quaternary baseband modulation www.datasheet.co.kr datasheet pdf - http://www..net/
functional description preliminary v1.1 5 ? processing gain: 12 db ? data scrambler for spectral whitening and added security ? voice interface: 64 kbps pcm (mu-law, a-law) codec or 32 kbps adpcm ? data interface: 8-bit parallel bus with 30-byte deep dual-fifo and interrupt signals ? modes: full-duplex voice, full-duplex or half-duplex data ? embedded time-division-duplex (tdd) controller ? msk on-the-air modulation ? differential encoder/decoder with four programmable 32-bit pn sequences ? programmable station id code ? independent low-speed signaling channel ? signal quality indicator output (s/n) ? power saving features ? implementation: cmos, 3v, 3.3v, 5v, 44-pin pqfp 2. functional description the SS1101C is made up of six main functional modules. these include the parallel bus interface (pbi), the receiver, the transmitter, the time-division duplex (tdd) controller, the transmit and receive fifos, and the master clock generator. a block diagram is presented hereafter as figure 1. the pbi module supports bi-directional communication with a microprocessor. the receiver module performs all the digital signal processing required by the spread spectrum receiver, including de-spreading and demodulation. the transmit module generates the spread spectrum binary sequence for output to the rf modulator. the tdd controller includes logic implementing the time-division duplex protocol and various handshaking and interface signals. the transmit and receive fifos are used to buffer the transmit and receive data both in the voice and data modes. the master clock generator generates the clock signal required to drive the various modules of the SS1101C. these modules are described in more detail below. 2.1. pbi the parallel bus interface (pbi) allows the SS1101C to communicate bi-directionally with a microprocessor. during power-on, the SS1101C should receive the programming information from the microprocessor through the pbi. the SS1101C receives and sends the signaling channel data through the pbi. in the data mode the pbi module also provides a bi-directional data path between the microprocessor and the SS1101C. 2.2. receiver the receiver samples the incoming baseband signal at two samples per pn chip. the samples are correlated with four possible pn sequences in 64-bit parallel correlators. www.datasheet.co.kr datasheet pdf - http://www..net/
functional description 6 preliminary v1.1 the de-spreaded signal is demodulated via a digital phase locked loop. to reduce power consumption, the receiver is powered down while the SS1101C is transmitting and consumes peak power only during the brief period of initial acquisition. after acquisition, the receiver goes into tracking/detection mode. figure 1. SS1101C block diagram 2.3. transmitter the transmitter logic encodes two consecutive bits of data into one of four possible 32- bit pn sequences. these pn sequences are programmed by the microprocessor through the pbi. the transmitted pn sequence is further randomized by modulus-2 addition with a fixed 2047-bit long pn sequence. this operation smooths the output spectrum of the transmitted signal and eliminates discrete spectral components. during tdd operation, the transmitter is powered off during the portion of the cycle when the SS1101C is in receive mode in order to save power. the transmitter output is a tri-state buffer and is at high-impedance state during a receiving period. 2.4. tdd controller the time-division duplex (tdd) controller implements the ping-pong protocol that allows a full-duplex link to be emulated by a half-duplex radio. the tdd controller also generates the appropriate clock and control signals to other modules of the SS1101C. in tr tx fifo tdd rx fifo rcvr codec parallel pwr management master clock voice codec data ctl tx rx rf interface bus interface interface www.datasheet.co.kr datasheet pdf - http://www..net/
operational description preliminary v1.1 7 full-duplex mode, the tdd controller multiplexes and de-multiplexes the overhead bits with the data or voice bit-stream. the tdd controller also uses a digital phase locked loop to maintain an equal read and write rate to the fifos as to avoid fifo overflow or underflow. in addition, the tdd controller contains logic to generate the proper handshaking signals for both voice and data communication. 2.5. fifos the SS1101C includes a 30-byte transmit fifo and a 30-byte receive fifo to buffer the input and output data. the control signals for the fifos are generated by the tdd controller. in the data modes the fifos provide the interrupt signals for the microprocessor and the microprocessor must read and write data to and from the fifos through the pbi. 2.6. master clock generator the master clock generator generates the various clock signals required by the modules described above. it can be disabled in power saving mode. 3. operational description in this section, the operation of the SS1101C in its various modes is described. 3.1. full-duplex voice and data operations although the SS1101C actually only uses a half-duplex channel for communication with the remote device, full-duplex operation is provided by using a time-division duplex (tdd) protocol. the tdd protocol basically configures the SS1101C alternatingly as a transmitter and as a receiver. when two devices are communicating with each other, one is programmed to be the master, while the other is programmed to be the slave. the tdd protocol ensures that while the master is transmitting, the slave is receiving and vice versa in a timely fashion. the end result is that as far as the user is concerned, the communication link appears to be full-duplex. in order to achieve this, it is necessary for the SS1101C to transmit at a higher rate than the actual user data rate. ideally, for tdd operation, with 100% efficiency and 0% overhead, the SS1101C must transmit the data at twice the user data rate since the SS1101C has only half the time to transmit the user data (during the other half time period, the SS1101C is receiving from the remote station). overhead such as preamble, unique word (uw), as well as other signaling information bits result in the SS1101C transmitting at 2.6 times the effective user data rate. the size of the fifos on the SS1101C is designed to provide sufficient buffer during both transmit and receive operations so that underflow or overflow of the fifos does not occur. when communication between two devices first commences, the microprocessors must program one of the devices as the master and the other device as the slave. the master device transmits periodic bursts as soon as the reset signal, rst1_n, is released. the burst timing of the master is derived from its internal master clock oscillator and can be computed from (eq 1) below: www.datasheet.co.kr datasheet pdf - http://www..net/
operational description 8 preliminary v1.1 (eq 1) in (eq 1), f burst is the burst rate and f mosc is the master oscillator frequency. for a voice device using the 32 kbps adpcm codec, the required master oscillator frequency is 16.384 mhz with a burst rate of 85.333 kbps or a burst period of 11.719 m sec. note, this burst rate is the actual bit rate at which the SS1101C is transmitting during tdd operation, and is 2.667 times the user bit rate (32 kbps). as the transmitter uses a quadrature modulation scheme, the chip rate is 16 times the burst rate or (eq 2) where f chip is the chip rate and f mosc is the master oscillator frequency. effectively, the spread spectrum transceiver operates at 16 chips/bit or 32 bits/symbol where each symbol is composed of 2 bits. for a voice device using the 64kbps pcm codec the required master oscillator frequency is 32.768 mhz. the burst rate and the chip rate are also doubled in value. the total number of bits per burst is fixed and equal for both the master and the slave. the slave derives its burst timing from the master by detecting the uw pulse transmitted by the master. 3.1.1 tdd protocol initially, the two communicating devices need to establish sync. the tdd protocol achieves this by using a special handshaking protocol. the master first transmits an acquisition burst. the acquisition burst consists of 32 bits of preamble (binary 0s), followed by 230 bits of zero stuffing, and four 22-bit unique words (uw). when the slave receives the acquisition burst from the master correctly (by decoding the 4 consecutive uws), it sends an acquisition burst in response. when the master receives the acquisition burst, it sends an empty burst. an empty burst contains a 32-bit preamble followed by a single 22-bit unique word, and 296-bit of 1 (one stuffing). in response to the masters empty burst, the slave also sends an empty burst back to the master. when the master receives the empty burst from the slave, the communication link is considered to have been established and sync condition achieved. on the following burst, both the master and the slave start genuine data transmission by sending out data bursts. each of the data bursts contain a 32-bit preamble, followed by a 22-bit uw, a 8-bit signaling word (sw), and 288 bits of user data (be it pcm/ adpcm voice samples or data). the three different types of burst frame structures are shown in figure 2. f burst f mosc 192 ----------- - = f chip f mosc 12 ----------- -16f burst == www.datasheet.co.kr datasheet pdf - http://www..net/
operational description preliminary v1.1 9 figure 2. burst frame structures each burst cycle also includes 2 guard times to allow for both propagation and rf transceiver switching time. more specifically, g 1 is a 28-bit delay between the time the master stops transmission and the slave commences transmission; g 2 is a 28-bit delay between the time the slave stops transmission and the master commences transmission. these guard times allow for a minimum delay of 328 m sec delay (for a master oscillator frequency of 16.384 mhz). the total burst cycle is 768 bits long, including 12 bits internal delay (the transmitter turns off 6 bits after the last data bit is latched into the transmitter, the master and slave therefore contribute a total of 12-bit internal delay). during tdd operation, the receiver will go through several stages. initially, when the 4 uws of the acquisition burst has been received and decoded correctly, the receiver (either master or slave) declares locked. after the empty burst has been decoded, the receiver declares rlocked signifying that the remote device has locked. the behavior of the receiver after establishing the rlock condition depends on whether the internal state machine is turned on or not (determined by the setting of the ci_h[4] bit). when the state machine is turned off, transmission will be turned off whenever the uw is not detected. the slave then waits for a new acquisition burst while the master will start the acquisition cycle again by transmitting an acquisition burst. note that the master will continue to broadcast acquisition bursts until it has received a proper acquisition burst from the slave in response. the master will always revert back to the initial acquisition mode (broadcasting acquisition bursts), whenever it fails to detect the proper uws from the slave. zero stuffing acquisition burst frame structure empty burst frame structure data burst frame structure preamble data one stuffing uw uw uw uw preamble preamble uw uw sw signaling word (sw) 22 32 288 8 preamble data unique word (uw) field bits www.datasheet.co.kr datasheet pdf - http://www..net/
operational description 10 preliminary v1.1 figure 3. receiver lock state machine if the state machine is turned on, then the receiver will not declare lock loss right after uw has not been detected. instead, it will allow for uw errors in up to two further bursts before declaration lock loss. the state diagram for this lock state machine is shown in figure 3. in the figure, uw4det indicates the condition when the four uws have been detected during acquisition burst, uwdet indicate the condition where the single uw in empty and data bursts has been detected. m_sb is the programmed bit (ci_h[0]) which is a binary 1 when the SS1101C is programmed to be the master and a binary 0 when programmed as a slave. nmode is a signal generated by the receive logic when the digital phase locked loop in the receiver has achieved lock, it is similar to an rssi signal. note that the nmode signal is independent of the uw detection. physically, when nmode is asserted, it indicates that pn acquisition has been achieved. the locked and rlock states are as described previously. 3.1.2 system delay to calculate the delay through the system (see figure 3.), assume that the transmit fifo is almost empty at the end of a burst. then the next bit that enters the transmit fifo will experience a system delay (excluding propagation delay but including the internal logic delay) of approximately: (eq 3) where t g is the time delay due to guard time (note: g = g1 = g2 = 28bits), t pr is the time delay due to preamble, t uw is the time delay of the uw, t sw is the time delay for signaling word transmission, t dat is the time delay for data transmission, and t d is the internal logic delay. for a 32 kbps adpcm voice signal, with a master oscillator (mo) of 16.384 mhz, this system delay translates into 5.625 msec. nmode +m_sb .uw4det rlock 0 1 2 locked unlocked uwdet uw4det uwdet nmode +m_sb .uw4det +uwdet uwdet uwdet uwdet rlock rlock uwdet uwdet t delay 2t g t pr t uw t sw ++ + () t dat t d ++ = www.datasheet.co.kr datasheet pdf - http://www..net/
operational description preliminary v1.1 11 figure 4. system delay 3.2. voice mode timing information in the voice mode the SS1101C starts transmit and receive right after the rst1_n is released (assuming the chipsel_n is enabled). the SS1101C generates the appropriate clock signals for interfacing with a 32-kbps adpcm or 64-kbps pcm voice codecs. specifically, the mhz2_st pin delivers the 2.048 mhz bit clock and the fclk_rt pin delivers the 8 khz framing or sync clock to a codec. the timing diagram for the adpcm interface is shown in figure 5. below. details of the timing specification are presented in the timing section. for the pcm codec there are 8bits of data instead of 4 bits, and fclk_rt pulse is 8 mhz2_st pulses long. figure 5. adpcm interface timing for voice operation, it is necessary to lock the average rate of writing data into the fifos to the average rate of reading data from the fifos. since the number of bits per burst is fixed and so is the burst rate, this can be achieved by locking the sample clock onto the burst rate. for voice mode operation, the 8 kframes/sec clock is locked onto the burst rate by a digital phase-locked loop in the tdd control module. the phase-locked loop fine tunes the 8 kframes/sec clock delivered to the codec, so that exactly 72 frame pulses are delivered per adpcm burst and 36 frame pulses are delivered per pcm burst. during each frame pulse, the adpcm interface delivers and receives 4 bits of t delay dat pr uw sw dat pr uw sw g2 g1 dat pr uw sw master slave mhz2_st msb lsb fclk_rt data www.datasheet.co.kr datasheet pdf - http://www..net/
operational description 12 preliminary v1.1 data to and from the adpcm codec. the pcm interface delivers and receives 8 bits of data to and from the pcm codec. in the pcm mode operation, a mo of 32.768 mhz is required 3.3. data mode timing information 3.3.1 full duplex operations in full duplex mode, chips communicating with each other should have rts_n enabled. a chip which is configured as a master starts the acquisition procedure and data transmission. a slave is waits for a valid spread spectrum signal to arrive. the SS1101C transmits and receives data through txfifo and rxfifo buffers. the writing and reading of data to and from the fifos are supported by the pbi. the synchronization of the data exchange between the microprocessor and the SS1101C is provided by the use of the interrupt signal (irq_n). if ie[2] and ie[3] bits of the ie register are enabled, the irq_n pin low indicates that either the txshl bit from txfifo or rxshh bit from rxfifo is set. txfifo interrupt will be active if the txfifo index is below the programmed txshl and will remain active until the index is above the txshh. the rxfifo interrupt will be active if the rxfifo index is above the programmed rxshh and will remain active until the index is below the rxshl. thus the microprocessor must write data into the SS1101C for transmission when the irq_n is asserted by the txfifo, and it must read data from the SS1101C when the irq_n is asserted by the rxfifo. the difference in value between thresholds high and low should be at list two bytes. if irq_n low indicates that the txshl control bit is set, data bytes should be written into the txfifo. to avoid the overflow of the txfifo and loss of data, the maximum number of bytes to be written should not be more than (30 - txshl) bytes. the size of the burst is 288 bits or 36 bytes. if there is not enough users data to fill up a burst at the end of transmission of the users data, 0s will be sent automatically (when there is no data and transmission is enabled, all 0s will be sent). if irq_n low indicates that the rxshh bit is set, data bytes should be read from the rxfifo. the high level protocol should take care of the end of transmission to avoid a situation where some data can be held in the rxfifo indefinitely or lost by a later reset. the timing relationship between the data and interrupt signals for transmit and receive is shown in figure 6. below. the rate with which the mcu feeds data to the transmitter fifo depends on the values of the thresholds and the burst rates. 3.3.2 threshold value calculation the performance of the mcu should be considered when calculating the txshl and rxshh. the time required for transmission of txshl bytes out of tx fifo should be more than the time required by the mcu to write a new set of data into the tx fifo. www.datasheet.co.kr datasheet pdf - http://www..net/
operational description preliminary v1.1 13 accordingly, the time for the receiving of rxshh bytes from the channel should be more than the time required by the mcu to read the data set from the rx fifo. figure 6. full-duplex data interface timing a typical start-up of the data link is also shown in figure 7., note that the same diagram would also apply for the voice mode operation where the mhz2_st and fclk_rt timing have the timing relationship previously presented in figure 5. in the full-duplex mode the SS1101C when programmed as a master, starts transmission as soon as reset rst1_n is released (rts_n is enabled). as long as the master is powered-on the SS1101C will send out the acquisition burst and try to establish a communication link with a remote slave. thus, the communication channel is occupied as soon as the master resets, and this can occur before any data becomes available for transmission. once the communication link is established, even when there is no data to be transmitted, the master and slave will remain in communication with each other (sending out 0 in the data field) indefinitely or until the master is disabled. 3.3.3 half-duplex operation the half-duplex data mode is suitable for applications such as scada, wireless lan or portable devices. the SS1101C does not make any assumption about the higher level protocol and relies on these higher level protocols to provide the necessary framing, error correction, and preamble. the SS1101C will transmit and deliver the data stream without multiplexing any protocol overhead bits, as it is the case for the full-duplex operation. ie[2] ie[3] irq_n data rdn wrn www.datasheet.co.kr datasheet pdf - http://www..net/
operational description 14 preliminary v1.1 it is the users responsibility to ensure that each packet transmitted contains enough preamble bits so that acquisition can be achieved prior to actual data delivery. similarly, although the SS1101C delivers the interrupt signals to the user, the user needs to be aware that in the half-duplex mode the SS1101C in the receiver mode (rts_n is disabled) delivers the interrupt signals even if there is no data received. all 0s will be read from the rxfifo in this case. also, invalid received data will be present at the output due to hysteresis of the digital phase-locked loop. thus, the user must be able to detect the end-of-packet from the data received rather than relying on the SS1101C to signify loss of the interrupt signal or loss of the lock. the SS1101C in the transmit mode (rts_n is enabled) will transmit 0 if there is no data in the txfifo. because no overhead in multiplexing is required, in half-duplex mode, the highest data rate supportable is equivalent to the burst rate of the full-duplex mode. for example using a mo of 30.72 mhz this can be set at 170 kbps. the relationship between the data rate and the required mo is as followed: (eq 4) the data exchanges through the pbi remain unchanged from those of the full-duplex operation. the rts_n bit designates the direction of transmission. the transmission is directed from a chip with rts_n enabled to a chip with rts_n disabled. to change the direction of transmission the value of rts_n should be reversed. note that, in the half- duplex mode, when rts_n changes value the SS1101C resets itself. the transmitter stops transmission as soon as rts_n is disabled. it is up to the user to include and detect end-of-packet information so that invalid data is not erroneously perceived as valid data. finally, note that there is no provision for csma/cd type collision avoidance in the hardware, it is up to the user or the modem system to implement any desired collision avoidance schemes either in hardware and/or software. a typical timing diagram for half-duplex operation is shown in figure 8. note that there is a key difference between full-duplex and half-duplex operation. in a half-duplex operation, there is no concept of master or slave. the SS1101C will start transmitting 0s (if there is no data in the txfifo) or data once the user has asserted the rts_n control bit. the SS1101C receiver will receive 0s or data, accordingly. the SS1101C receiver will generate the interrupt signals and deliver 0s to the mcu even if there is no transmission process at all. those 0s are stored in the rxfifo f data f mosc 192 ----------- - = www.datasheet.co.kr datasheet pdf - http://www..net/
operational description preliminary v1.1 15 . figure 7. typical communication link start-up figure 8. timing for half-duplex operation acquisition burst acquisition burst empty burst master slave g2 data burst g1 empty burst data burst data burst rlock locked uwdet_n transmit receive rlock locked uwdet_n * drawing not to scale. modout di rts_n rts_n invalid rx data ~60 bits receiver acquisition ~60 bits transmitter receiver www.datasheet.co.kr datasheet pdf - http://www..net/
the parallel bus interface 16 preliminary v1.1 4. the parallel bus interface the parallel bus (pbi) is designed to interface the SS1101C with a generic microprocessor. the pbi supports the loading of the SS1101C programmable data from the microprocessor, generates interrupts for remote signaling and s/n data and is used for bi-directional data transfers in data mode. in the following sections, the operation of the interface is discussed in more detail. 4.1. read and write operations the read/write access time of the SS1101C is less than 25ns in the worst case. 4.1.1 write operation 1. the microprocessor latches the data into the appropriate registers for both the address and data bus signals and by providing the wrn signal. 2. both address and data shall be stable before wrn goes to low, and remain stable until wrn becomes inactive (1). the write timing diagram is shown below. figure 9. pbi write operation 4.1.2 read operation 1. the microprocessor reads the pbi data from the appropriate register on the data bus by providing data on the address bus together with the rdn signals. wrn d[7:0] chipsel_n rdn addr[3:0] www.datasheet.co.kr datasheet pdf - http://www..net/
the parallel bus interface preliminary v1.1 17 2. the address shall be stable before rdn goes to low, and remain stable until rdn becomes inactive (1). figure 10. pbi read operation 4.2. loading of the SS1101C programmable data the microprocessor configures the SS1101C by loading the SS1101C control registers with the programmable information including pn sequences, unique word, configuration information bits, test bits, signaling word, etc. after the microprocessor selects the SS1101C by setting the chipsel_n to lo, the loading of the SS1101C is done by the following steps: 1. after power up the contents of the control registers are not defined. the micropro- cessor writes the appropriate values into the intended register using the write operation. 2. the microprocessor resets the SS1101C using rst1_n pin (assert the system reset pin rst1_n for some time and then release it to inactive 1) wrn d[7:0] addr[3:0] chipsel_n rdn www.datasheet.co.kr datasheet pdf - http://www..net/
the parallel bus interface 18 preliminary v1.1 . figure 11. loading of the SS1101C programmable data 4.3. reading the sw and s/n data from the pbi the signaling word (sw) and s/n registers in full duplex voice and data modes are updated periodically by the SS1101C: ? the signaling word is updated once every burst ? the s/n data is calculated from the agc circuit inside the SS1101C once every 128 data bits (including overhead bits) to read the signaling word or the s/n value, the pbi read operation needs to be performed. 4.3.1 signaling word (sw) transmitting if no sw value has been loaded at the time the communication starts (lock is achieved), the signaling word (sw) transmit register will be filled with an ff byte and this value will be transmitted with each burst. once a signaling word has been written into the register, it is transmitted with the next burst. if there is no new signaling word written, the current signaling word value will be transmitted with each next burst, until a new sw is loaded for transmission. 4.3.2 sw receiving the ie[0] bit in the ie control register, when asserted, enables the receive sw interrupt. if the interrupt was not enabled before the communications started, it is possible to enable it during the transmission. the SS1101C should be reset after the interrupt is enabled during the communication. wrn d[7:0] addr[3:0] chipsel_n rdn rst1_n www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers preliminary v1.1 19 when the interrupt is enabled, once a signaling word has been received and loaded onto the signaling word receive register, the interrupt irq_n is asserted. if the interrupt was not serviced, a new byte will be loaded into the register on the next burst. the previous byte will be lost. if the received data is needed, the interrupt should be serviced between bursts. 5. control, sw, and fifo registers a total of thirty-one registers are available for storing and retrieving the various programming parameters and data through the pbi. they are listed below: table 1. control, sw, and fifo registers name address index bank select ci_l[1] write/ read functions ci_l 0000 [7:0] 0 low wr/ rd ci_l[0]: normal mode ci_l[1]: high/low bank select ci_l[3:2]:width of esd window ci_l[4]: set the width of central region ci_l[5]: dpll accumulator 1 reset ci_l[7:6]: set the width of detection window ci_h 0001 [7:0] 0 low wr/ rd ci_h[0]: master/slave selection bit ci_h[3:1]:number of errors allowed in the uw ci_h[4]:locksmon ci_h[5]:data/voice mode selection ci_h[6]: 64/32kbit select in voice mode, semi/full duplex select in data mode ci_h[7]:rts_n bit (0 to enable) fifo 0010 [7:0] 0 low wr/ rd write data for txfifo read data for rxfifo ie 0011 [3:0] 0 low wr ie[0]: enable the rxsw received interrupt ie[1]: enable the s/n interrupt ie[2]: enable the txfifo interrupt ie[3]: enable the rxfifo interrupt is 0011 [3:0] 0 low rd is[0]: rxsw interrupt pending is[1]: s/n interrupt pending is[2]: txfifo interrupt pending is[3]:rxfifo interrupt pending www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers 20 preliminary v1.1 txsw 0110 [7:0] 0 low write signaling word to be transmitted rxsw 0110 [7:0] 0 low read signaling word received s/n 0111 [7:0] 0 low read signal/noise indicator pna0 1000 [7:0] 0 low wr/ rd pna[7:0] pna1 1001 [7:0] 0 low wr/ rd pna[15:8] pna2 1010 [7:0] 0 low wr/ rd pna[23:16] pna3 1011 [7:0] 0 low wr/ rd pna[31:24] pnb0 1100 [7:0] 0 low wr/ rd pnb[7:0] pnb1 1101 [7:0] 0 low wr/ rd pnb[15:8] pnb2 1110 [7:0] 0 low wr/ rd pnb[23:16] pnb3 1111 [7:0] 0 low wr/ rd pnb[31:24] uw0 0001 [7:0] 1 high wr/ rd uw[7:0] uw1 0010 [7:0] 1 high wr/ rd uw[15:8] uw2 0011 [7:0] 1 high wr/ rd uw[21:16] table 1. control, sw, and fifo registers name address index bank select ci_l[1] write/ read functions www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers preliminary v1.1 21 5.1. configuration information bits the configuration information bits are used to set the various programmable parameters in the SS1101C: ci_l[0] should be set to lo. ci_l[1] selects high/low bank. high= high bank; low= low bank ci_l[3:2] plsl. sets the width of the esd window. ci_l[2] is lsb, ci_l[3] is txshh 0100 [4:0] 1 high wr/ rd transmitting fifo interrupt threshold high txshl 0101 [4:0] 1 high wr/ rd transmitting fifo interrupt threshold low rxshh 0110 [4:0] 1 high wr/ rd receiving fifo interrupt threshold high rxshl 0111 [4:0] 1 high wr/ rd receiving fifo interrupt threshold low pnc0 1000 [7:0] 1 high wr/ rd pnc[7:0] pnc1 1001 [7:0] 1 high wr/ rd pnc[15:8] pnc2 1010 [7:0] 1 high wr/ rd pnc[23:16] pnc3 1011 [7:0] 1 high wr/ rd pnc[31:24] pnd0 1100 [7:0] 1 high wr/ rd pnd[7:0] pnd1 1101 [7:0] 1 high wr/ rd pnd[15:8] pnd2 1110 [7:0] 1 high wr/ rd pnd[23:16] pnd3 1111 [7:0] 1 high wr/ rd pnd[31:24] table 1. control, sw, and fifo registers name address index bank select ci_l[1] write/ read functions www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers 22 preliminary v1.1 msb. see application section. ci_l[4] cntlr. sets the width of the central region. ( note : cntlr size must be plsl size).see application section. ci_l[5] acc1res. dpll accumulator 1 reset. see application section. ci_l[7:6] wsl. sets the width of the detection window. ci_l[6] is lsb, ci_l[7] is msb. see application section. ci_h[0] m/sb. set the SS1101C to be a master (hi) or slave (lo). note: must be set to lo in half-duplex data mode. ci_h[3:1] t. number of errors allowed in the uw. ci_h[1]is lsb, ci_h[3] is msb. plsl width of esd window 0 8 samples wide 1 10 samples wide 2 12 samples wide 3 14 samples wide cntlr width of central region 0 10 samples wide 1 12 samples wide acc1res accumulator1 reset 0 acc1 not reset. 1 reset acc1. wsl width of detection window 0 4 samples wide 1 6 samples wide 2 8 samples wide 3 10 samples wide t allowable uw errors 00 bit 11 bit 2 2 bits 3 3 bits 4-7 4 bits www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers preliminary v1.1 23 ci_h[4] locksmon. enables the locking state machine when set to hi (see figure 3. for locking state machine state diagram). ci_h[5] selects data or voice modes: hi (1) selects data; lo (0) selects voice ci_h[6] selects operation mode: for voice: hi (1) is 64 kbps, lo (0) is 32 kbps. for data hi (1) is half-duplex, lo (0) is full-duplex ci_h[7] rts_n bit value: lo (0) enables rts, hi (1) disables rts fifo receive (rxfifo) and transmit (txfifo) registers. one address is used to access both registers. the wrn and rdn signals are used to access the required register. the read/write operations are described in section 4.1. read and write operations. ie interrupt enable. enables interrupts for rxsw, s/n, txfifo, and rxfifo. if more than one interrupt is enabled and interrupts are generated, the irq_n pin goes low. all interrupts are ored to the irq_n pin. to service the interrupts the is register should be read. all interrupts, but rxsw, can be enabled during the transmission, without resetting the SS1101C. is indicates the source of an interrupt or interrupts if the interrupts are enabled in the ie register. the interrupts do not have priorities. it is up to the users software to define the sequence for servicing the interrupts. 5.2. reset the SS1101C contains one external reset control signal rst1_n. the rst1_n is used to reset the SS1101C and to disable the clocks. the rst1_n reset signal does not affect the values stored in the control registers. an internal source of reset is the ci_h[7] bit (rts_n) of the ci_h control register. when the rts_n bit status is changed the SS1101C is reset. 5.3. rf/if analog interface the SS1101C interfaces with the rf/if analog radio through the following pins: di, modout, pllsw, txen and rfpwr. di is a cmos-level input fed by the analog receiver. modout is a tri-state output to the analog transmitter. it is in high-impedance state when the SS1101C is in the receive mode (txen is lo). pllsw and rfpwr are used respectively to switch the pll of the analog radio and to power on/off the transmitter power amplifiers. the timings for the rfpwr and pllsw are shown in figure 12. and figure 13. respectively. www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers 24 preliminary v1.1 the rfpwr switch timing is designed to avoid damage to the sensitive analog receiver. when switching from receive to transmit, rfpwr is delayed relative to txen (which can be used for switching the antenna between transmit and receive chain) to ensure that the receiver has been turned off before the transmitter is turned on. similarly, when switching from transmit to receive, rfpwr is turned off first, before txen, to allow extra time for the transmitter to turn off prior to turning on the receiver circuits. note that the rfpwr timing is valid for both full-duplex and half-duplex modes. the burst_clk shown in figure 12. is the burst rate clock which is 2.667 times the data rate in full-duplex operation and is equaled to the data rate in half-duplex operation. for example, for a master oscillator of 16.384 mhz, the full-duplex burst rate is 85.333 khz. thus, the rfpwr signal will be asserted one burst clock cycle or 11.72 m sec after txen assertion and will be de-asserted one burst clock cycle or 11.72 m sec prior to txen de-assertion. the pllsw timing shown is for the full-duplex mode; for half-duplex operation, pllsw timing follows that of the rfpwr. the pllsw signal is designed to switch the rf pll when different frequencies are used for transmit and receive operation. in this instance, pllsw is turned on right at the end of receive operation and prior to txen assertion to allow the rf pll to stabilize. similarly, the pllsw changes to a lo as soon as transmission is finished and before receiving commences. figure 12. rfpwr timing the pllsw is asserted 28 burst clock cycles (duration of g2) prior to txen assertion and is de-asserted 1 burst clock cycle before txen is de-asserted in the full-duplex mode. thus, for a master oscillator of 16.384 mhz (corresponding to a burst rate of 85.333 khz or a burst period of 11.719 m sec), the pllsw signal will be asserted 328 m sec (28*11.72=328) prior to txen assertion. t burst _ clk burst_clk txen rfpwr t burst_clk www.datasheet.co.kr datasheet pdf - http://www..net/
control, sw, and fifo registers preliminary v1.1 25 figure 13. pllsw timing (full-duplex mode) g2 t burst_clk txen pllsw receive transmit receive not drawn to scale. note: g2=28xt burst_clk www.datasheet.co.kr datasheet pdf - http://www..net/
i/o description 26 preliminary v1.1 6. i/o description vdd input volts dc. note, the SS1101C can operate with either a 3.0-volt, a 3.3-volt or a 5.0-volt dc power supply. however, the SS1101C will not operate reliably in a mixed voltage environment. vss input. ground. osci16 input. to be used for an operating frequency between 10mhz and 24mhz. input to the on-chip crystal oscillator. when a crystal is used, it is expected to be connected across osci16 and osco16 pins. if a crystal clock oscillator or an external clock source is used, then osci16 should be connected to the clock source and osco16 left opened. any external clock source (or crystal clock oscillator) should have % duty cycle and ppm accuracy. osco16 output. 10mhz - 24mhz oscillator output. output of the on-chip crystal oscillator. should be connected to one side of a crystal or left opened if an external clock source or crystal clock oscillator is used. osci32 input. to be used for an operating frequency between 20mhz and 60mhz. input to the on-chip crystal oscillator. when a crystal is used, it is expected to be connected across osci32 and osco32 pins. if a crystal clock oscillator or an external clock source is used, then osci32 should be connected to the clock source and osco32 left opened. any external clock source (or crystal clock oscillator) should have % duty cycle and ppm accuracy. osco32 output. 20mhz - 60mhz oscillator output. output of the on-chip crystal oscillator. should be connected to one side of a crystal or left opened if an external clock source or crystal clock oscillator is used. clksel input. oscillator 16 or oscillator 32 enable. when low enables a crystal connected to osci16-osco16. when high enables a crystal connected to osci32-osco32. the unused set of input pins should be grounded (osci32 and osco32 should be grounded when using osci16-osco16 and vice versa. 3.0 0.25 /3.3 0.25 /5.0 0.25 50 0.25 50 50 0.25 50 www.datasheet.co.kr datasheet pdf - http://www..net/
i/o description preliminary v1.1 27 clken input. oscillators enable. enables the on-chip crystal oscillators when asserted, otherwise, the on-chip crystal oscillators are disabled. oscup output. microprocessor clock. this is a clock signal generated internally from the master oscillator. it is a divide-by-4 version of the master oscillator. for example, when using a 16.384 mhz master oscillator, the oscup pin delivers a 4.096 mhz clock. its main purpose is to reduce the required number of clock signals for the system. tx input. tx pin accepts the adpcm/pcm sample input from a codec. rx output. the SS1101C delivers the received adpcm/pcm samples to a codec. mhz2_st output. the mhz2_st pin delivers the 2.048 mhz bit rate clock signal to the adpcm or pcm codec. note, the SS1101C latches tx data on the falling edge of mhz2_st. fclk_rt output. the fclk_rt pin delivers the 8 khz framing clock to the adpcm/pcm codec. bsync_out output. burst sync output. burst synchronization pulse. can be used in a wireless pbx environment, where several radios are co-located, to synchronize the burst timing, thereby reducing far-near interference. bsync_in input. burst sync input. to be externally looped back to bsync_out or to an external burst timing source. rfpwr output rf power switch. designed to switch the transmitter on when asserted and off when de-asserted. discussed in more detail in the operational section. pllsw output phase-lock loop switch. designed to switch the transceiver synthesizer between tx and rx frequencies. it is asserted for tx and de-asserted for rx. see operational section for more detail. www.datasheet.co.kr datasheet pdf - http://www..net/
i/o description 28 preliminary v1.1 txen output transmitter enable. when asserted, connects the antenna to the transmitter. when lo, connects the antenna to the receiver. modout output modulation output. spread spectrum modulated chip output. di input. received data input. cmos compatible input from the analog receiver. rst1_n input. reset. when lo resets the storage elements in the SS1101C and freezes all clocks except the master oscillator. chipsel_n input. chip select. when lo validates the address on the address bus. when hi, the SS1101C ignores all activity on the address bus. addr[3:0] inputs. pbi address bus. msb is bit 3, lsb is bit 0. used to select the address of the control registers or fifos for reading or writing data. irq_n output. indicates that there is an interrupt. to identify the source of the interrupt the content of the is register should be read. d[7:0] bi directional. pbi data bus. msb is bit 7, lsb is bit 0. used for reading or writing of external data. rdn input. pbi external data read strobe wrn input. pbi external data write strobe www.datasheet.co.kr datasheet pdf - http://www..net/
i/o buffer information preliminary v1.1 29 7. i/o buffer information in this section, the dc characteristics of the i/o buffers are presented. note: tbd - to be defined i/o type i/o characteristics osco output vol min = vss, vol max = 0.4 v voh min = 2.4 v, voh max = vdd 0 ma < iol <6.0 ma -5.5 ma < ioh < -0 ma output vol min = vss, vol max = 0.4 v voh min = 2.4 v, voh max = vdd iol = 2 ma, ioh = -2 ma (vdd = 5.0) iol = 1 ma, ioh = -1 ma (vdd = 3.0) input vil min = vss, vil max = 0.3*vdd vih min =.7*vdd, vih max = vdd iil min = -1 m a, iih max = 1 m a bi-direc- tional tbd table 2. i/o buffer dc characteristics www.datasheet.co.kr datasheet pdf - http://www..net/
timing information 30 preliminary v1.1 8. timing information information regarding selected waveforms is presented in this section. general timing these are valid for all pins unless specified otherwise. 9. absolute maximum rating 10. recommended operating conditions note: * denotes estimated value. parameter symbol min. nom. max. unit setup time t setup 0 1.17 2.54 ns hold time t hold 00.501.18 ns pulse width t width 1.25 ns table 3. general ac timing information parameter symbol value unit dc supply voltage v dd C v ss -0.3 to 7.0 v voltage, any pin to v ss v in -0.3 to v dd + 0.3 v dc current, any pin (except v dd and v ss )i 10 ma operating temperature range t a 0 to 70 c storage temperature range t stg -55 to 150 c table 4. absolute maximum rating parameter symbol min. nom. max. unit dc supply voltage v dd 2.7 3.0/3.3/5.0 5.5 v power dissipation at 5v p dis 15 90 130 mw master oscillator f osc 5-40 60 * mhz table 5. recommended operating conditions www.datasheet.co.kr datasheet pdf - http://www..net/
system performance preliminary v1.1 31 11. system performance a significant number of the system performance parameters depend heavily on the rf/ analog circuits. the information presented here therefore represents only an estimate of these parameters. parameter estimated performance oscillator stability depends primarily on the analog circuitry but < 15 ppm over temperature range and aging (for 1 db sensitivity degradation) should be achievable. acquisition time < 100 bits average < 200 bits for 99.9% probability of acquisition at s/n of 2 db (applies for first burst only). interference immunity in channel ( 1.365 mhz) -6 db j/s worst case cw jammer to signal power ratio sensitivity in white noise (half-duplex mode) 19.0 db e b /n 0 for ber = 10 -5 . 17.5 db e b /n 0 for ber = 10 -4 . 16.5 db e b /n 0 for ber = 10 -3 . estimated power dissipation (5 volt operation) 50.7 mw average in tdd mode at 32 kbps full-duplex 76.8 mw average in tdd mode at 64 kbps full-duplex estimated power dissipation (3 volt operation) 15.0 mw average in tdd mode at 32 kbps full-duplex table 6. system performance www.datasheet.co.kr datasheet pdf - http://www..net/
pin assignment 32 preliminary v1.1 12. pin assignment figure 14. pin assignment 13. application information in this section, several application issues concerning the use of the SS1101C are discussed. 13.1. notes on half-duplex operation the receiver will not be locked until the initial acquisition process has been completed. this process typically takes from 60-110 bits depending on the condition of the radio link. it is imperative, therefore, for the packet to carry framing information so that the beginning and end of the packet can be detected (for example, a high-speed synchronous data link protocol such as hdlc provides its own framing structure in the packets it transmits). clksel osco16 osci16 vss nc nc nc nc vdd modout txen d6 d7 oscup rx tx fclk_rt mhz2_st clken rst1_n osco32 osci32 d5 d4 d3 d2 nc nc nc d1 d0 wrn rdn addr0 addr1 addr2 addr3 irq_n chipsel_n di pllsw rfpwr bsync_out bsync_in index corner 44-pin pqfp www.datasheet.co.kr datasheet pdf - http://www..net/
application information preliminary v1.1 33 in addition, sufficient preamble bits must be transmitted prior to actual data transmission so that the receiver will be locked and ready to deliver data when actual data arrives. the chip will generate rxfifo interrupts after the lock is achieved. the interrupt can be generated even if there is no data sent by the transmitting side. a transmitting chip with no data to send continuously sends all 0s, this will lock a receiving chip and continuously generate the rxfifo interrupt on the receiving side. the txfifo interrupt should be disabled in a receiving chip, while the rxfifo interrupt should be disabled in the transmitting chip. this should be done to avoid the need to service any non-useful interrupts. 13.2. selecting the master oscillator frequency a complete clock generator has been included in the SS1101C as to reduce the system clocking requirement. nominally, only a single crystal or clock oscillator is required for powering the entire SS1101C. the required crystal or clock oscillator frequency is dependent on the data rate and in general can be calculated from the following equations: (eq 5) where f osc is the master oscillator frequency, f codec is the bit-rate clock of the codec, and f data is the data rate. for example, for a 32 kbps adpcm voice, f codec = 32khz, and the required f osc is 16.384 mhz. for 64 kbps full-duplex data, f data = 64 kbps and the required master oscillator frequency is 32.768 mhz. for 170 kbps half-duplex data, f data = 170 kbps and the required master oscillator frequency is 30.72 mhz. 13.3. programming the SS1101C in the following, a brief discussion on programming the SS1101C for the various modes of operation is presented. first, the loading of the pn sequences a, b, c, d and uw is required for operation in all modes. the programming of the plsl, cntlr, acc1res, and wsl depend on several environmental and system related factors. for example, the sizing of plsl and cntlr windows involves trade-off considerations in the plls dynamic performance. in general, if smaller window size is used, the pll will behave as if it has a smaller loop bandwidth with higher noise filtering but at the expense of slower dynamic response. if larger window size is used, the pll will respond quicker dynamically but its performance will be degraded because more noise is allowed to enter the system. please note that the width of the central zone must be smaller than or equal to the size of the esd window (this means that the esd window size should not be set to 8, it was included on the chip for testing purpose only) . similarly, the width of the detection window, wsl, should be large enough to take advantage of multipath combining but should not be so large that excessive noise is allowed into the receiver causing receiver sensitivity degradation. in general, these f osc 192 2.6667xf codec for full-duplex voice == f osc 512 f data for full-duplex data = f osc 192 f data for half-duplex data = www.datasheet.co.kr datasheet pdf - http://www..net/
application information 34 preliminary v1.1 parameters can be experimentally optimized for a particular environment. otherwise, it is recommended that these parameters be programmed to values in the middle of the programmable range (for example, set plsl to 12 samples wide, cntlr to 10 samples wide, and wsl to 8 samples wide). in the full-duplex or tdd mode, acc1res should normally be set to 0 for no acc1 reset during each freeze pll period. the only instance where acc1res should be set 1 to reset acc1 is if the frequency offset between the transmitter and receiver is known to be very small. in this case, the performance of the pll will be slightly enhanced if acc1 is reset during each freeze pll period. in half-duplex operation. acc1res should be set to 1 to always reset acc1. ci_h[0] is used to set the SS1101C to be either a master or a slave. typically, in a cordless phone application, the unit (either the handset or the base station) that initiates the signalling process should be programmed to become the master. thus, when dialing into the pstn (public switched telephone network), the handset unit is configured to be the master and when receiving an incoming phone call, the base station is configured as the master. note, for half-duplex operation, ci_h[0] must be set to lo (e.g., as a slave). there is no concept of master or slave in the half-duplex operation. instead, the SS1101C is keyed by the rts_n bit enable to go into transmit mode. the SS1101C stays in the receive mode otherwise. the number of allowable errors in uw depends on the application. for example, applications that can tolerate a larger ber can usually allow more uw errors while still maintaining a reasonable communication link as in the case of voice applications. finally, ci_h[4] enables or disables the locking state machine. the locking state machine when used in conjunction with the programmable allowable uw errors gives the system designer the flexibility to tailor the SS1101C for a particular operating environment. typically, by enabling the locking state machine and by allowing more uw errors, the SS1101C will continue to operate normally even in a marginal communication link channel without repeatedly loosing lock and going into acquisition. the disadvantage is the corresponding increase in the data errors; for some critical applications, this might not be tolerable. in this case, the number of allowable uw errors can be reduced and the locking state machine turned off. www.datasheet.co.kr datasheet pdf - http://www..net/
application information preliminary v1.1 35 figure 15. sample block diagram for a cordless phone system in figure 15., a simple cordless phone system block diagram is shown. note that the setup in the base station will be slightly different than that for the handset. for simplicity, only a generic block diagram is shown. figure 16. sample block diagram for a data modem in figure 16, a sample block diagram for use as a data modem is shown. sst SS1101C microprocessor telephone vo i c e rf mo mhz2_st tx rx fclk_rt txen/ rfpwr/ plsw modout di interface codec pbi SS1101C microprocessor rf mo irq1_n txen/ rfpwr/ plsw modout di rst1_n bsync addr[3:0] oscup d[7:] www.datasheet.co.kr datasheet pdf - http://www..net/
application information 36 preliminary v1.1 13.4. pn sequence and uw selection four 32-bit pn sequences and one 22-bit unique word (uw) are required for each spread spectrum communication device. together, they can constitute a security code or identification code which can be use to distinguish different users as well as to provide privacy. in addition, the pn sequences and uw participate in the signal acquisition and burst synchronization processes. in order to ensure good system performance, the pn sequences and uw must be selected with some care. in the following, guidelines for choosing the pn sequences and uw are presented. 13.4.1 pn sequence selection the four pn sequences are used to represent a di-bit symbol in the SS1101C. in order to correctly decode the transmitted symbol at the receiver, the following principles should be followed when choosing the four pn sequences. 1. the four pn sequences should be orthogonal to each other. two pn sequences a and b are orthogonal to each other if, (eq 6) where pn sequence a = [a 31 , a 30 , a 29 ,, a 1 , a 0 ], for , and for ; similarly for b. 2. the pn sequences should be even, i.e., each sequence should have the same number of zeros and ones. 3. the pn sequences should not have more than four consecutive identical bits. with these three criteria outlined above, it is possible to generate a large set of valid pn sequences. two additional and optional criteria can be used to further identify pn sequences for reduced self- and cross-interference. 1. the auto-correlation side lobes of the pn sequences should be less than the auto- correlation of the main lobe by at least 4. 2. the cross-correlation of pn sequences between sets (one set being the four orthogo- nal pn sequences for one spread spectrum chip) should also be less than the auto- correlation of the main lobe by at least 4. 13.4.2 uw selection the uw is used in the receiver in full-duplex mode to establish synchronization. to avoid interference, the uw must be chosen such that it has good auto-correlation and cross-correlation properties. the auto-correlation of a sequence a denoted as s n is defined as, (eq 7) where l is the length of the sequence a, , , for , and for . a window version of s n can also be defined as per (eq 7) with the exception that , where w is the window size. the desired auto-correlation a i b i i0 = 31 ? 0 = a i 1 C =a i 0 =a i 1 = a i 1 = s n a i a in C i0 = l ? = l Cnl << n0 1 a i 1 C =i0 < a i a i22 C =il 3 0nw << www.datasheet.co.kr datasheet pdf - http://www..net/
application information preliminary v1.1 37 property is that the maximum value of the auto-correlation s n (with or without the window where the window size is the size of the detection window, wsl) is less than , where t is the allowable number of uw errors programmed into the SS1101C. the cross-correlation of two sequences a and b, denoted by r n is defined as, (eq 8) where l is the length of the sequence, , and for . as before, the desirable cross-correlation property is that the maximum value of the cross- correlation r n is less than , where l and t are as defined previously. requirements for choosing good uws can be thus summarized by the following equations. (eq 9) for example, when t is programmed to be 4, then s n and r n should be less than 14 since l is 22. 13.5. generating the pn and uw sequences there are many ways of generating the pn and uw sequences, including brute force search of the complete code space. a more efficient but probably not optimal way of generating the pn and uw sequences is to 1. generate the m and gold sequences of order n where (eq 10) and where l is the length of the pn or uw sequence. 2. because m and gold sequences are only bits long, it is necessary to append an additional bit to these sequences so that they are 2 n bits long. the additional bit should be chosen such that the modified m or gold sequence is even. 3. apply the criteria outlined in the previous sections to pick out the good set of pn and uw sequences. 13.6. using burst synchronization feature the SS1101C contains a burst synchronization feature that allows multiple chips to transmit and receive signals synchronously. by synchronizing their bursts, the interference amongst these units is greatly reduced. in order for the burst synchronization feature to work correctly, the SS1101Cs must be setup appropriately. first, a master must be chosen so that the other devices derive their timing from it. for the master, the burst_out signal is connected to its own burst_in signal as well l2t C r n a i b in C i0 = l ? = 0n l < b i b i22 + =i0 < l2t C s n l2t C < r n l2t C < nl 2 log = 2 n 1 ? www.datasheet.co.kr datasheet pdf - http://www..net/
application information 38 preliminary v1.1 as to the burst_in signals of the other devices. this establishes burst-level synchronization by forcing the burst cycle of each device to follow that of the master. 13.7. example of rf front-end block diagram in the following page an example of rf block diagram for the SS1101C chip is presented. this block diagram is an example of rf front-end architecture; it uses minimum- frequency shift modulation (msk / fsk). other architectures are also possible using the SS1101C chip. the chip rate depends on the data rate and the mode (duplex or half-duplex) of the application: other data rates are possible up to the half-duplex maximum of 400 kbps for the SS1101C. the filters as shown in the block diagram should be specified as follows: the antenna band-pass filter should cover the complete frequency range, for instance, 902 - 928 mhz. the receiver if bpf should be 20% wider than twice the chip rate. by making it somewhat wider, you can avoid excessive group delay distortion at the band edges. the lpf following the discriminator should have a 3 db cutoff frequency around the chip rate. the lpf preceding the synthesizer should also have its 3 db cutoff frequency around the chip rate. the bandwidth of the phase-lock loop of the synthesizer should not be wider than 0.75% of the chip rate. that way it will not suppress modulation at 3% of the chip rate and above. mode application bit-rate chip rate msk bandwidth full-duplex voice or data 32 kbps 1.365 mbps 2.048 mhz full-duplex data 50 kbps 2.133 mbps 3.200 mhz full-duplex voice or data 64 kbps 2.731 mbps 4.096 mhz half-duplex data 32 kbps 512 kbps 768 khz half-duplex data 50 kbps 800 kbps 1.200 mhz half-duplex data 64 kbps 1.024 mbps 1.536 mhz www.datasheet.co.kr datasheet pdf - http://www..net/
application information preliminary v1.1 39 frequency stability: within 50 khz for the total chain: transmit and receive units. this should be easy to achieve. www.datasheet.co.kr datasheet pdf - http://www..net/
synthesizer transmitter tr switch bpf lpf xtal osc lna bpf modout di txen rfpwr pllsw txen chip SS1101C up converter lpf example of msk radio rf front-end 715 mhz 902-928 mhz fm discriminator if bpf if = 21.4 mhz transmit: 200.0 mhz receive: 178.6 mhz www.datasheet.co.kr datasheet pdf - http://www..net/

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